SiC MOSFETS AND SELF-ALIGNED FABRICATION METHODS THEREOF

ABSTRACT

The present application provides a method of fabricating a metal oxide semiconductor field effect transistor. The method includes the steps of forming a source region on a silicon carbide layer and annealing the source region. A gate oxide layer is formed on the source region and the silicon carbide layer. The method further includes providing a gate electrode on the gate oxide layer and disposing a dielectric layer on the gate electrode and the gate oxide layer. The method further includes etching a portion of the dielectric layer and a portion of the gate oxide layer to form sidewalls on the gate electrode. A metal layer is disposed on the gate electrode, the sidewalls and the source region. The method further includes forming a gate contact and a source contact by subjecting the metal layer to a temperature of at least about 800° C. The gate contact and the source contact comprise a metal silicide. The distance between the gate contact and the source contact is less than about 0.6 μm. A vertical SiC MOSFET is also provided.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional of U.S. patent application Ser. No. 12/483,469, filed Jun. 12, 2009 which a continuation-in-Part of U.S. patent application Ser. No. 11/593,317, filed on Nov. 6, 2006, wherein the applications are incorporated herein in their entirety by reference.

BACKGROUND

The invention relates generally to methods of fabricating silicon carbide based metal oxide field effect transistors (MOSFETs) and in particular to self-aligned methods of fabricating silicon carbide based MOSFETs.

Silicon carbide (SiC) is an attractive alternative to silicon (Si) for high voltage, high power applications due to the inherent material properties of SiC. For example, SiC exhibits a wide band gap and a high thermal conductivity that facilitates elevated temperature operation.

For certain devices such as, SiC vertical metal oxide field effect transistors (MOSFET), close packing of adjacent cells is desirable, to enhance on-resistance and switching performance. To increase cell packing density, the spacing between the gate and source contacts must be reduced. However, a reduction in the gate to source contact spacing typically reduces the manufacturable yield of SiC MOSFETs.

Therefore, it is desirable to provide a method that addresses these issues related to the spacing between gate and source contacts in vertical SiC MOSFETs. It is also desirable to increase the manufacturable yield of closely packed vertical MOSFET devices. Accordingly, a technique is needed to address one or more of the foregoing problems in the fabrication of SiC MOSFET devices.

BRIEF DESCRIPTION

In one aspect, a method of fabricating a metal oxide semiconductor field effect transistor is provided. The method includes the steps of forming a source region on a SiC layer and annealing the source region. A gate oxide layer is formed on the source region and the SiC layer. The method further includes providing a gate electrode on the gate oxide layer and disposing a dielectric layer on the gate electrode and the gate oxide layer. The method further includes etching a portion of the dielectric layer and a portion of the gate oxide layer to form sidewalls on the gate electrode. A metal layer is disposed on the gate electrode, the sidewalls and the source region. The method further includes forming a gate contact and a source contact by subjecting the metal layer to a temperature of at least about 800° C. The gate contact and the source contact comprise a metal silicide. The distance between the gate contact and the source contact is less than about 0.6 μm.

In another aspect, a vertical SiC metal oxide semiconductor field effect transistor (MOSFET) is provided. The SiC MOSFET includes a SiC layer having a source region. A gate oxide layer is disposed on the SiC layer and extends over at least a portion of the source region. The MOSFET includes a gate electrode disposed on the gate oxide layer and a gate contact disposed on the gate electrode. The gate contact comprises metal silicide. The MOSFET further includes a source contact extending over at least a portion of the source region. The source contact comprises metal silicide, and the distance between the gate contact and the source contact is less than about 0.6 μm.

In yet another aspect, a method is provided that includes providing a silicon carbide layer, a gate oxide layer (e.g., silicon dioxide, silicon nitride, or glass forming material) on the silicon carbide layer, and a gate electrode including silicon on the gate oxide layer (e.g., a polycrystalline silicon or “polysilicon”-including gate electrode). A conductive layer can be disposed adjacent to the gate electrode, the conductive layer being configured to electrically contact a gate voltage source. The conductive layer may be disposed such that the conductive layer extends substantially along a long dimension of the gate electrode. The silicon carbide layer, the gate oxide layer, the gate electrode, and the conductive layer may be subjected together to a temperature in a range of about 800 degrees Celsius (° C.) to about 1100° C. The silicon carbide layer may be configured to act as a MOSFET. The MOSFET can be operated with the conductive layer disposed on the gate electrode.

The conductive layer can be a metal layer, such as, for example, tantalum, nickel, cobalt, titanium, molybdenum, tungsten, niobium, hafnium, zirconium, vanadium, chromium, and/or platinum, or can be a metal silicide layer, such as, for example, silicides of the above metals. In one embodiment, tantalum silicide can be sputtered from a tantalum silicide source using a power of about 0.5 kW to 2.5 kW, an argon working gas as a pressure of about 5 mTorr to 25 mTorr.

In still another aspect, a device is provided that includes a semiconductor layer including silicon carbide. A gate oxide layer can be disposed on the semiconductor layer. A gate electrode including silicon can be disposed on the gate oxide layer, the gate electrode having a long dimension. The gate electrode can be configured to electrically contact a gate voltage source such that currents through the gate electrode that are induced by the voltage source are directed substantially transverse to the long dimension of the gate electrode. In one embodiment, the device may further include a conductive layer on the gate electrode, the conductive layer being configured to electrically contact a gate voltage source so as to establish electrical contact between the gate voltage source and said gate electrode.

DRAWINGS

These and other features, aspects, and advantages of the present invention will become better understood when the following detailed description is read with reference to the accompanying drawings in which like characters represent like parts throughout the drawings, wherein:

FIGS. 1-6 illustrate fabrication stages of a vertical SiC MOSFET, according to example embodiments;

FIGS. 7-14 illustrate fabrication stages of a vertical SiC MOSFET, according to another example embodiment;

FIGS. 15 and 16 schematically depict the operation of the vertical SiC MOSFET fabricated as shown in FIGS. 7-14; and

FIG. 17 schematically depicts the operation of a typical MOSFET.

DETAILED DESCRIPTION

It will be understood by those skilled in the art that “n-type” and “p-type” refer to the majority of charge carriers, which are present in a respective layer. For example, in n-type layers, the majority carriers are electrons, and in p-type layers, the majority carriers are holes (the absence of electrons). As used herein, n+ and n refer to higher (greater than 1×10¹⁸ cm⁻³) and lower (generally in the range of 5×10¹⁵ cm⁻³ to 5×10¹⁷ cm⁻³) doping concentrations of the dopants, respectively.

As used herein, the term “about” should be understood to indicate plus or minus fifty percent (+/−50%).

A MOSFET is a type of transistor that includes a gate, a drain and a source. The source and drain of a typical MOSFET are formed of a semiconducting substrate such as Si. For SiC MOSFETs, the semiconducting substrate comprises SiC. The gate is separated from the substrate by an insulating layer. As will be appreciated, upon application of a voltage or an electric field across the gate, the source to drain current can be controlled. The current generated is then transferred from the substrate through respective gate and source contacts.

The performance of a MOSFET is to a large extent dependent on the gate and source contacts. It is desirable that the gate and source contacts are electrically and structurally stable during operation and also that they offer minimal ohmic resistance to passage of current. Moreover, by reducing the distance or spacing between the source contact and the gate contact in a MOSFET, the size of the MOSFET may be reduced and more of such MOSFETs may be packed within, for example, an integrated chip. Advantageously, the increase in packing density may enhance the on-resistance and switching performance of the device. The methods for enhancing the packing density may suffer from one or more limitations. For example, the methods for reducing the distance between the source contact and the gate contact may inadvertently cause the shorting of these contacts due to poor alignment.

Example embodiments of the present invention are described below in detail with reference to the accompanying drawings, where the same reference numerals denote the same parts throughout the drawings. Some of these embodiments may address the above and other needs.

Turning now to the figures, FIGS. 1-6 illustrate fabrication stages of a vertical SiC MOSFET 10, according to embodiments of the present invention. FIG. 1 is a cross-sectional side view of a vertical SiC MOSFET 10. The SiC MOSFET 10 includes a semiconductor layer 12 having a drift region 14 disposed thereon. The semiconductor layer 12 may be a semiconductor substrate on which other materials are formed, disposed and/or patterned. Alternatively, semiconductor layer 12 may be an intermediate layer of a device being fabricated on an underlying substrate. The semiconductor layer 12 may be a semiconductor material such as, Si, SiC, aluminum nitride, sapphire, or gallium nitride, for example. Further, the semiconductor layer 12 may be a polytype of SiC, such as 4H—SiC, or 6H—SiC polytypes. The semiconductor layer 12 may be p-type doped, or n-type doped or even undoped. In the illustrated embodiment, the semiconductor layer 12 is of 4H—SiC and is n-type doped. The semiconductor layer 12 may have a thickness of about 350-550 micrometers (μm) and a dopant concentration of about 5×10¹⁸ ions/cm³, for example. In certain embodiments, the thickness of the semiconductor layer 12 may be in a range of about 200 μm to about 600 μm. In some embodiments, the dopant concentration of the semiconductor layer 12 may be in a range of about 1×10¹⁸ ions/cm³ to about 1×10²¹ ions/cm³.

The drift region 14 is of SiC. Further, the drift region 14 may be a polytype of SiC, such as 4H—SiC, or 6H—SiC polytypes. In the illustrated example of the MOSFET 10 having an n+ doped source region, the drift region 14 is n-type doped with n-type dopants such as nitrogen, phosphorus, or any combinations thereof As will be appreciated, for a MOSFET 10 having a p+ doped source region, the drift region 14 may be doped with p-type dopants including boron, aluminum, gallium, carbon, or any combinations thereof The dopants may be introduced during the formation of the drift region 14, for example. In some embodiments, a deposition technique such as, chemical vapor deposition (CVD) may be performed to form the drift region 14. Alternatively, an epitaxial growth of the semiconductor layer 12 is performed to form the drift region 14, and the dopants are introduced during the epitaxial growth. The drift region 14 may have a doping concentration in a range of about 1×10¹⁴ ions/cm³ to about 1×10¹⁶ ions/cm³. In one embodiment, the drift region 14 is about 12 μm thick and is of 4H—SiC with an n-type doping level of about 9×10¹⁵ ions/cm³.

In the drift region 14, P-well regions 16 are formed. The P-well region 16, in one embodiment, is formed by ion implantation of p-type dopants such as boron, aluminum, gallium, carbon, or any combinations thereof in the drift region 14. As will be appreciated, the formation of p-well region 16 may involve a number of processing steps such as, masking the drift region 14 by a first mask, and patterning the first mask prior to ion implantation in the drift region 14. In one embodiment, the masking is by the application of a photoresist over the drift region 14. The applied photoresist is then patterned by forming openings, wherein the openings correspond to an area of the P-well region 16. Through the openings in the photoresist the p-type dopant ions are implanted in the drift region 14 to obtain the P-well regions 16. In one embodiment, subsequent to the formation of P-well region 16, the photoresist is removed. Alternatively, a second mask may be applied on the first mask prior to ion implantation to form a source region 18 in the P-well region 16. The implanted p-type dopants are then annealed at elevated temperatures to electrically activate the implanted ions. In one embodiment, the annealing temperature is greater than about 1100° C. In some embodiments, the annealing temperature is in a range of about 1100° C. to about 1900° C. Typically, the concentration of the implanted ions in the P-well region 16 is greater than that of the drift region 14 to facilitate implantation of p-type dopants in the n-doped drift region 14. In one embodiment, the concentration of the p-type dopants in the P-well region 16 is greater than about 1×10¹⁶ ions/cm³. In certain embodiments, the concentration of the p-type dopants in the P-well region 16 is in a range of about 1×10¹⁶ ions/cm³ to about 5×10¹⁸ ions/cm³.

The n+ source region 18 is formed in the P-well regions 16. In one embodiment, a second mask is applied after the removal of the first mask and may include processes as described with reference to the first masking process. The n-type dopants are implanted in the P-well region 16 through the openings in the second mask, for example, in a method involving the masking technique. Example n-type dopants include nitrogen, phosphorus, or any combinations thereof The n+ source region 18 has a dopant concentration greater than about the concentration of the p-type dopants in the P-well region 16. In some embodiments, the dopant concentration in the n+ source region 18 is greater than about 1×10¹⁸ ions/cm³. In certain embodiments, the dopant concentration in the n+ source region 18 is in a range of about 1×10¹⁸ ions/cm³ to about 1×10²¹ ions/cm³. Subsequent to the formation of the source region 18, the implanted n-type dopants are annealed at elevated temperature so as to activate the implanted ions. In one embodiment, the annealing temperature is greater than about 1650° C. In some embodiments, the annealing temperature is in a range of about 1100° C. to about 1900° C.

A drain region 20 may be provided on a surface of the semiconductor layer 10 opposite to the drift region 14. In some embodiments, the drain region 20 forms part of the semiconductor layer 12 which is heavily n-type doped. The concentration of the dopants in the drain region 20, in some embodiments, is greater than about 1×10¹⁸ ions/cm³. In certain embodiments, the concentration of the dopants in the drain region 20 is in a range of about 1×10¹⁸ ions/cm³ to about 1×10²¹ ions/cm³.

A gate oxide layer 22 is disposed on the source region 18, the P-well regions 16 and on the drift region 14. The formation of the gate oxide layer 22, in one example, is through thermal oxidation of the drift region 14. In another example, a low temperature chemical vapor deposition (CVD) technique is used to form the gate oxide layer 22. The gate oxide layer comprises silicon dioxide (SiO₂), silicon nitride or other glass forming materials. Non-limiting examples of glass forming materials include borosilicate glass or phosphosilicate glass. Typical thickness of the gate oxide layer 22 is less than about 200 nanometers. In some embodiments, the thickness of the gate oxide layer 22 is in a range of about 20 nanometers to about 200 nanometers.

A gate electrode 24 is disposed on the gate oxide layer 22. Exemplary gate electrode 24 materials include metals and polysilicon. The deposition of the gate electrode 24, in one embodiment, is performed using physical vapor deposition (PVD) techniques such as sputtering or evaporation. Alternatively, a chemical vapor deposition technique may be utilized. The gate electrode 24 covers a portion of the gate oxide layer 22. The remaining uncovered portion of the gate oxide layer 22 corresponds to a future location of a source contact. Typically, the thickness of the gate electrode 24 is about 0.5 μ. In some embodiments, the thickness of the gate electrode 24 is in a range of about 0.1 μm to about 1.0 μm.

As shown in FIG. 2, a dielectric layer 26 is disposed on the gate electrode 24 and the gate oxide layer 22. The dielectric layer 26 forms a thin layer around the gate electrode 24 and may advantageously protect the gate electrode 24 from damages from subsequent processing steps. In exemplary embodiments, the dielectric layer 26 comprises silicon dioxide or silicon nitride. In one embodiment, the deposition of the dielectric layer 26 is through thermal oxidation of the gate electrode 24. Following thermal oxidation, the dielectric layer 26 is annealed at temperatures greater than about 1100 degrees Celsius. Alternatively, a chemical vapor deposition technique may be employed. The thickness of the dielectric layer 26 may play a part in determining the distance between a source contact and a gate contact. In some embodiments, the thickness of the dielectric layer 26 is greater than about 0.5 μm. In one embodiment, the thickness of the dielectric layer 26 is in a range of about 0.1 μm to about 1.0 μm.

The dielectric layer 26 and the gate oxide layer 22 are then subjected to etching such that a portion of the gate oxide layer 22 and a portion of the dielectric layer 26 are removed so as to form sidewalls 28 on the gate electrode 24, as shown in FIG. 3. In one embodiment, the etching is performed using a dry etch process. In one embodiment, the dry etch is through a reactive ion etch (RIE) method. In the reactive ion etch method, etchants such as CF₄ and O₂ are used, which preferentially etches the gate oxide layer 24 and the dielectric layer 26 while the etchants CF₄ and O₂ have minimal action towards the drift region 14. The portion of the gate oxide layer 24 and the portion of the dielectric layer 26 are etched away to form the sidewalls 28. According to embodiments of the present invention, the width of the sidewalls 28 is advantageously used to control the distance between a gate contact and a source contact.

FIG. 4 depicts a metal layer 30 disposed on the gate electrode 24, the sidewalls 28 and over the P-well region 16 and the source region 18. In one embodiment, the deposition of metal layer 30 is through PVD techniques such as sputtering or evaporation. In another embodiment, the metal layer 30 is deposited using a chemical vapor deposition technique. In a particular embodiment, the metal layer comprises nickel. In other embodiments, the metal layer 30 comprises cobalt or titanium. The metal layer 30 is deposited as a thin layer. In some embodiments, the thickness of the metal layer 30 is in a range of about 25 nm to about 500 nm. In certain embodiments, the thickness of the metal layer 30 is in a range of about 25 nm to about 55 nm. In one particular embodiment, the thickness of the metal layer 30 is about 55 nm.

The metal layer 30 is then subjected to high temperature annealing to form metal silicide layers 32 and 34 (layers 32 and 34 are the future source and gate contacts, respectively), respectively, as shown in FIG. 5. The metal reacts with Si to form the respective metal silicide. For example, when the metal layer 30 comprises nickel, then the layers 32 and 34 comprise nickel silicide. In other embodiments, the metal silicide comprises cobalt silicide or titanium silicide. The metal layer 30 in contact with the underlying Si at the source region 18 reacts to form the metal silicide layer 32. Similarly, the metal layer 30 in contact with the underlying Si at the gate electrode 24 form the metal silicide layer 32. As will be appreciated, the sidewalls 28 comprising the dielectric material, for example, silicon dioxide shows no activity towards the metal and hence there is no metal silicide formation on the sidewalls 28. According to embodiments of the present invention, the distance between the metal silicide layers 32 and 34 is to a large extent dependent on the width of the sidewalls 28. In one embodiment, the distance between the metal silicide layers 32 and 34 is less than about 0.6 μm. In some embodiments, the distance between the metal silicide layers 32 and 34 is in a range of about 0.1 μm to about 1.0 μm.

In one embodiment, the metal layer 30 is annealed at a temperature of at least about 800° C. In some embodiments, the annealing temperature is in a range of about 800° C. to about 1100° C. In one example, the metal layer 30 is annealed at a temperature of about 1050° C. for 3 minutes in nitrogen. Exemplary anneal times are in a range of about 1 minute to about 30 minutes. The composition of the metal silicide layers 32 and 34, and in turn the quality of the resultant ohmic contacts to a certain extent depends on the annealing temperature. Typically, nickel silicide contacts are formed at temperatures lower than about 700° C. to avoid undesirable changes in the underlying layers. For example, high temperature annealing may result in diffusion of dopants from a source region to a substrate which may decrease the efficiency of the device.

According to embodiments of the invention, an annealing temperature of greater than about 800° C. may result in a better contact than the contact formed at temperatures below about 700° C. Although, the applicant does not wish to be bound by any particular theory, it is believed that the high temperature anneal may form a metal silicide phase that may lower the ohmic resistance at the interface between the SiC and the metal silicide and hence may result in a better contact.

The metal silicide layers 32 and 34 may have a thickness of at least about 55 nm, in one embodiment. In some embodiments, the thickness of the metal silicide layers 32 and 34 is in a range of about 25 nm to about 500 nm.

The remaining metal (that is on the sidewalls 28) is then etched to form the source contact 32 and the gate contact 34, respectively, as depicted in FIG. 6. The etching is through a wet-etching process that preferentially etches the metal while leaving the source contact 32 and the gate contact 34 behind.

The source contact 32 and the gate contact 34 are typically used to provide low resistance contacts for the source region 18 and the gate electrode 24. In one embodiment, at least one of the source contact 32 and the gate contact 34 has a contact resistivity of less than about 10⁻⁵ ohm/cm⁻². In some embodiments, at least one of the source contact 32 and the gate contact 34 has a contact resistivity in a range of about 10⁻³ ohm/cm⁻² to about 10⁻⁶ ohm/cm⁻².

The SiC vertical MOSFET 10 formed using above-described embodiments advantageously has a spacing of less than about 0.6 μm between the source contact and the gate contact. In some embodiments, the spacing between the source contact and the gate contact is in a range of about 0.1 μm to about 1.0 μm. Moreover, using self-aligned methods may provide a better alignment of the source contact and the gate contact with respect to the each other, and with the respect to the source region and the gate region, thus avoiding undesirable shorting effects that reduces the manufacturable yield of the MOSFETs.

Referring to FIGS. 7-14, therein is schematically shown fabrication stages of a vertical SiC MOSFET 110 configured in accordance with another example embodiment. The SiC MOSFET 110 includes a semiconductor layer 112 having a drift region 114 disposed thereon (see FIG. 7). In the illustrated embodiment, the semiconductor layer 112 is of 4H—SiC and is n-type doped. The semiconductor layer 112 may have a thickness of about 350-550 μm and a dopant concentration of about 5×10¹⁸ ions/cm³, for example.

The drift region 114 is of SiC. In the illustrated example where the MOSFET 110 has an n+ doped source region, the drift region 114 is n-type doped. As discussed above, the dopants may be introduced during the formation of the drift region 114, for example, by CVD or epitaxial growth onto the semiconductor layer 112. The drift region 14 may have a doping concentration in a range of about 1×10¹⁴ ions/cm³ to about 1×10¹⁶ ions/cm³. In one embodiment, the drift region 114 is about 12 μm thick and is of 4H—SiC with an n-type doping level of about 9×10¹⁵ ions/cm³.

In the drift region 114, P-well regions 116 are formed (FIG. 7). The P-well regions 116 may be formed, for example, by ion implantation into the drift region 114 and subsequent annealing, as discussed above. The n+ source region 118 can then be formed in the P-well regions 116, for example, using ion implantation followed by annealing, and similarly a drain region 120 may be provided on a surface opposite to the drift region 114 (FIG. 7).

A 20-200 nm gate oxide layer 122 can be disposed on the source region 118, the P-well regions 116 and on the drift region 114 (FIG. 8). The formation of the gate oxide layer 122 can be, for example, through thermal oxidation of the drift region 114 or low temperature CVD. The gate oxide layer can include SiO₂, silicon nitride, or other glass forming materials (e.g., borosilicate glass, phosphosilicate glass). A polysilicon gate electrode layer 124 can then be disposed, via PVD or CVD on the gate oxide layer 122 (FIG. 9). The thickness of the gate electrode layer 124 can be, for example, in a range of about 0.1 μm to about 1.0 μm. The polysilicon gate electrode layer 124 may then be doped, for example, using ion implantation or high temperature diffusion from a gas source, in order to increase the conductivity thereof

A patterned metal layer 130 can then be disposed adjacent to, in the illustrated case on, the gate electrode 124 (FIG. 10). The deposition of metal layer 130 (typically an initially blanket metal layer) can be through, for example, PVD, CVD, and or plating of a blanket film followed by patterning (discussed below). The metal layer 130 may include, for example, tantalum, nickel, molybdenum, cobalt, titanium, and/or other transition metal elements, and can have a thickness, for example, ranging from about 25 nm to about 500 nm. In one embodiment, the metal layer 130 may be formed of tantalum deposited via sputtering.

Deposition of the (typically blanket) metal layer 130 can be followed by patterning of the metal using standard positive or negative photolithographic techniques. The metal layer 130 can be patterned such that the metal layer can, ultimately, electrically communicate with a gate voltage source V_(G) (see FIG. 15). In some embodiments, the metal layer 130 may be annealed prior to patterning, for example, at a temperature ranging from 300° C. to 700° C., although in other embodiments such an anneal is eliminated. Thereafter, the patterned metal layer 130 can be used as a mask layer in order to etch the underlying polysilicon gate electrode layer 124 and the oxide layer 122 (FIGS. 11 and 12). Alternatively, the same masking layers that allow patterning of the metal layer 130 (e.g., a photoresist layer (not shown) over the metal layer) can be retained for patterning the polysilicon layer 124 and, in some cases, the oxide layer 122.

Metal 131 can then be disposed over the p-well regions 116 and the source regions 118 (FIG. 13). For example, the metal 131 (which can be the same as or different from the metal used for layer 130) could be deposited as a blanket layer and then patterned via photolithography. The MOSFET 110 may then be subjected to high temperature annealing at a temperature ranging from 300° C. to 1100° C. (e.g., about 1050° C. for 3 minutes in nitrogen). This annealing causes the formation metal silicide layers 132 and 134, as shown in FIG. 14, as the metal 130, 131 reacts with the respectively underlying Si and SiC and both the metal layers 130, 131 and the Si/SiC are at least partially consumed. For example, the metal 130 may include tantalum, in which case the layer 134 may include tantalum silicide. The relative concentration of Si may vary spatially within the metal silicide layers 132, 134, such that Si content may be higher in areas close to the initial metal-Si or metal-SiC interface and may decrease when moving away from the initial metal-Si or metal-SiC interface and toward the metal 130, 131. “Metal silicide” is therefore understood to refer to a range of metal-Si alloys rather than a specific alloy designation. Further, while distinct boundaries are shown between the metal silicide layers 132, 134 and the metal layers 130, 131, these boundaries may be diffuse

In some embodiments, metal silicide layers may be produced by depositing (and patterning, possibly after heat treating at a temperature ranging from 300° C. to 700° C.) the metal silicide material (about 10-1000 nm in thickness) directly onto the underlying polysilicon gate and/or SiC substrate, rather than by inducing a reaction between a metal layer and underlying Si/SiC. The metal silicide material can be, for example, sputter deposited either from a metal silicide source or from metal and Si sources in parallel. For example, tantalum silicide can be produced by sputter deposition from either a TaSi₂ target or from separately powered Si and Ta sputter targets. The process parameters for depositing the tantalum silicide can include. The sputtering can be carried out, for example, a single pass with a 6 cm/min scan rate, at a power of about 2 kW and using argon (Ar) as the working gas at a pressure of 20 mTorr. Films deposited using these process parameters may be suitable for subsequent reactive ion etching (i.e., may show regular sidewalls following such etching). Other possible metal silicides that may be sputtered or otherwise deposited include, for example, silicides of nickel, cobalt, titanium, and/or platinum. In still other embodiments, a mixture of metal and Si may be co-deposited onto the Si gate and/or SiC substrate, after which a heat treatment can be performed to induce the diffusion of further Si into the metal or metal silicide layer from the underlying gate or substrate.

Eventually, electrical communication can be established between a gate voltage source V_(G) and the metal layer 130, between a source voltage source V_(S) and the metal layer 131, and between a drain voltage source V_(D) and the drain region 120 (FIG. 15). Thereafter, MOSFET 110 would be operational.

For embodiments in which the metal silicide layer 134 includes tantalum silicide deposited via sputtering according to the above process parameters, Applicants have observed that the resulting metal silicide layer may exhibit a reduced residual stress. The reduced residual stress tends to enhance the mechanical stability of devices incorporating the reduced-stress metal layer. For example, mechanical failure of the interface between the metal layer and the underlying polysilicon gate is inhibited. Such residual stresses may be further reduced in the case where tantalum silicide is deposited stoichiometrically, in which case volume changes during subsequent annealing may be reduced, thereby potentially enhancing thermal stability at temperatures above 700° C. This aspect may be advantageous in cases where high temperature processing and/or operation of devices is desired or required, as may often be the case for SiC-based semiconductor devices. High-temperature processing is necessary in SiC devices for formation of ohmic contacts to the SiC and for re-flow treatments of inter-layer dielectric (ILD) films, both of which typically require heat treatments at temperatures ranging from about 800° C. to about 1100° C. Therefore, SiC devices require materials, such as silicides (for example, tantalum silicide, as observed by the Applicants) that are stable at high temperatures. This is in contrast to standard Si-based semiconductor devices, for which processing and operation temperatures are often limited to less than 450° C. in order to avoid detrimentally affecting the device junction depth.

MOSFET embodiments that include metal, metal silicide, or other low resistance materials over the gate may exhibit a lower effective electrical resistance of the gate structure of the device (hereinafter referred to as the “gate resistance” and/or R_(gate)). Referring to FIG. 16, one reason for this lowering of the effective gate resistance is that charge that is applied to the gate electrode 224 by the gate voltage source V_(G) (and through, in this case, the metal pad 240) tends to be applied, via the intermediate conductive layer 234 (e.g., a layer of metal silicide), more completely across the surface S_(G) of the gate. This effect may be enhanced by disposing the conductive layer 234 substantially along the long dimension L_(G) of the gate electrode 224. As a result, transient currents I_(e) through the gate electrode 224 are directed substantially along a direction transverse to the long dimension L_(G) (e.g., in the illustrated case, along the thickness t_(G) of the gate electrode), and have only a small directional component along the long dimension L_(G) of the gate electrode. The current can spread along the long dimension L_(G) via a current I_(c) through the conductive layer 234. This is in contrast to the typical case, depicted in FIG. 17, in which charge is supplied to the gate electrode from the gate voltage source via a more localized point of electrical contact, from which point the charge must spread laterally through the gate electrode. This laterally-directed current may result in a longer current path through the gate electrode itself, and where the gate electrode is a somewhat resistive material, such as Si, a higher effective resistance. As such, it may be advantageous in some embodiments to have the intermediate conductive layer 234 extend along the long dimension L_(G) to an extent sufficient to have more than a trivial impact on the current profile through the gate electrode 224.

In some embodiments, the MOSFET gate can be thought of as a distributed resistance-capacitance network. Configuring the gate as a long stripe that is contacted at one end by a gate voltage source may facilitate MOSFET formation, but can also lead to an elongated gate structure with a correspondingly increased gate resistance. Further, the gate typically rests atop a thin gate dielectric layer, so that there is significant capacitance between the gate and the underlying semiconductor substrate. When the gate voltage source applies a voltage V_(G) at one end of the gate, that same voltage does not appear at the other end of the gate until some time later. The time required for the entire gate to reach the voltage V_(G) becomes shorter as the resistance of the gate is reduced, and therefore, the turn on and turn off times of the MOSFET will be limited by the resistance of the gate electrode. After the gate resistance is reduced below a certain low value, for example by placing a layer of low resistance tantalum silicide in intimate contact with the higher resistance polysilicon gate as described above, the MOSFET turn on time will become mainly limited by the rise time of the voltage applied to the device, and is relatively independent of the gate resistance. Therefore, reducing the gate resistance can be important in producing a fast switching MOSFET.

In some embodiments, the lowering of the effective gate resistance may reduce switching losses associated with MOSFET operation. Specifically, for example, during the operation of a half-bridge power circuit, the associated switches can undergo fast transients of the drain voltage during the switching of devices from on to off. During this switching transient, the drain voltage rises quickly, which causes displacement current I_(gate) to flow through the gate-drain capacitance and the gate resistance and to the gate drive. This displacement gate current can cause a voltage drop between the gate terminal and output of the gate drive, the magnitude of this voltage drop being equal to the product I_(gate)*R_(gate). When this displacement gate current-induced voltage drop exceeds the MOSFET threshold voltage, the affected switch will inadvertently turn on. Such transient MOSFET activation events can result in increased switching losses and electromagnetic interference of the circuit (EMI).

The above described problem, while potentially of limited importance for Si-based devices, is exacerbated for SiC-based devices. More specifically, power semiconductor device efficiency relates to both the power dissipated by the device when conducting current (conduction losses) and the power dissipated while switching states, e.g., from conducting to non-conducting (switching losses). Ideal switches would minimize both power loss mechanisms to maximize the transfer of energy, through the device, between source and load. For power applications where high voltage and high frequency switching are required, it has been found that unipolar devices provide the preferred solution (e.g., Schottky diodes and MOSFETs). The alternative, bipolar devices, (e.g., PIN diodes, insulated gate bipolar transistors, and thyristors) have switching speeds that are limited by carrier recombination processes and are inherently slower, increasing the switching losses. In Si technology, efficient unipolar devices are found with ratings up to about 600 volts, above which voltage the Si thickness and doping levels required makes them prohibitively resistive (leading to unacceptably high conduction losses). This same cross over voltage does not occur in SiC until about 3000 volts due to the thinner material layers and higher doping possible for a given voltage rating. Thus efficient unipolar devices are possible for the >600 volts to 3000 volt range using SiC-based devices. However, Applicants have observed that operation in this regime introduces a greater sensitivity to gate resistance than usually seen for Si-based devices.

While the above-described issue may be of limited importance for Si-based devices, the problem can be exacerbated for SiC MOSFETs (relative to Si-based devices), for several reasons. First, the SiC MOSFET gate-drain capacitance density tends to be larger (due to typically higher doping levels and MOSFET channel packing density). Second, in SiC technology it is often advantageous to dope the polysilicon gate as p-type, but the resistance of p-type polysilicon is about four times higher than that for n-type polysilicon.

While only certain features of the invention have been illustrated and described herein, many modifications and changes will occur to those skilled in the art. For example, while some of the above described MOSFET embodiments have focused on a gate electrode having a conductive layer disposed along a top surface of the gate, in other embodiments the conductive layer may extend along a side surface of the gate. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the invention. 

What is claimed:
 1. A device comprising: a semiconductor layer including silicon carbide; a gate oxide layer disposed on the semiconductor layer; a gate electrode including silicon disposed on the gate oxide layer, the gate electrode having a long dimension; wherein said gate electrode is configured to electrically contact a gate voltage source such that currents through the gate electrode that are induced by the voltage source are directed substantially transverse to the long dimension of the gate electrode.
 2. The device of claim 1, wherein said gate oxide layer includes at least one of silicon dioxide, silicon nitride, or glass forming material.
 3. The device of claim 1, wherein said gate electrode includes polysilicon.
 4. The device of claim 1, further comprising a conductive layer on the gate electrode, the conductive layer being configured to electrically contact a gate voltage source so as to establish electrical contact between the gate voltage source and said gate electrode.
 5. The device of claim 4, wherein said conductive layer includes at least one of a metal layer, a metal silicide layer, or adjacent metal and metal silicide layers.
 6. The device of claim 4, wherein said conductive layer includes a metal silicide layer selected from the group consisting of tantalum silicide, nickel silicide, cobalt silicide, titanium silicide, molybdenum silicide, tungsten silicide, niobium silicide, hafnium silicide, zirconium silicide, vanadium silicide, chromium silicide, and platinum silicide.
 7. The device of claim 4, wherein said conductive layer includes at least one of tantalum, nickel, cobalt, titanium, molybdenum, tungsten, niobium, hafnium, zirconium, vanadium, chromium, or platinum.
 8. The device of claim 4, wherein said conductive layer extends substantially along the long dimension of the gate electrode. 